Many integrated circuits require an external clock signal to control sequential logic, switched-capacitor filters, or the like. The clock signal must be amplified and buffered on-chip in order to drive a large number of clocked circuits. In some very-large-scale integration (VLSI) devices it is necessary to minimize high-frequency interference caused by harmonics contained in a square wave input clock signal. For these devices, the input clock signal is preferably a sinusoidal signal of relatively small amplitude, such as one volt peak-to-peak, which is alternating current- (AC-) coupled through a capacitor to a clock amplifier. The clock amplifier typically includes an inverter which is self-biased to keep the direct current (DC) voltage on the input node near the switchpoint of the inverter.
An important feature for integrated circuits is to be able to operate in a low-power or "sleep" mode. In the low-power mode, most circuitry is disabled to save power and this circuitry does not need to be clocked. Upon re-entering normal operation, this circuitry again needs a clock signal for proper operation. It is desirable for the integrated circuit to disable as much circuitry as possible during low-power mode and to recover quickly from low-power mode. These performance requirements create a tradeoff for the clock amplifier. If the clock amplifier is disabled during low-power mode, then the coupling capacitor may discharge and the output of the clock amplifier will not switch while the coupling capacitor is recharging. However, the amplifier is always biased near its switchpoint during operation, resulting in a significant DC current. Thus, if the clock amplifier remains enabled during low-power mode, power consumption increases. A clock amplifier circuit which avoids these tradeoffs is needed.